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1 tft-lcd supply + dcp + vcom amplifier + gate pulse modulator + reset isl97649b the isl97649b is an integrated power management ic (pmic) for tft-lcds used in notebooks, tablet pcs, and monitors. the device integrates a boost converter for generating a vdd . v on and v off are generated by a charge pump driven by the switching node of the boost. the isl97649b also includes a v on slice circuit, reset function , and a high performance vcom amplifier with dcp (digitally cont rolled potentiometer) that is used as a vcom calibrator. the a vdd boost converter features a 1.5a /0.18 boost fet with 600/1200khz switching frequency. the gate pulse modulator can control gate voltage up to 30v, and both the rate and slew delay time are selectable. the supply monitor generates a reset signal when the system is powered down. the isl97649b provides a programmable vcom with i 2 c interface. one vcom amplifier is also integrated in the chip. the output of vcom is power-up with voltage at the last programmed 8-bit eeprom setting. features ? 2.5v to 5.5v input ? 1.5a integrated boost for up to 15v a vdd ?v on /v off supplies generated by charge pumps driven by boost switch node ? 600/1200khz selectable switching frequency ? integrated gate pulse modulator ? reset signal generated by supply monitor ? integrated vcom amplifier ?dcp -i 2 c serial interface, address:100111, msb left - wiper position stored in 8-bit nonvolatile memory and recalled on power-up - endurance, 1,000 data changes per bit ? uvlo, uvp, ovp, ocp, and otp protection ? pb-free (rohs compliant) ? 28 ld 4x5 qfn applications ? lcd notebook, tablet, and monitor pin configuration isl97649b (28 ld 4x5 qfn) top view en lx vin freq comp ss gpm_lo avdd scl sda pos rset fb pgnd ce re vgh vghm vflk nc cd2 nc reset nc vdiv neg 1 2 3 4 5 6 7 22 21 20 19 18 17 16 28 27 26 25 24 23 91011121314 vdpm 8 vout 15 gnd thermal pad caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. december 5, 2011 fn7927.0
isl97649b 2 fn7927.0 december 5, 2011 application diagram pin descriptions pin# symbol description 1 fb avdd boost converter feedback . connect to the center of a voltage divider between avdd and gnd to set the avdd voltage. 2pgndpower ground 3 ce gate pulse modulator delay control. connect a capaci tor between this pin and gnd to set the delay time. 4 re gate pulse modulator slew control. connect a resistor between this pin and gnd to set the falling slew rate. 5 vgh gate pulse modulator high voltage input. plac e a 0.1f decoupling capa citor close to vgh pin. 6 vghm gate pulse modulator output for gate drive ic. 7 vflk gate pulse modulator control input from t con . 8 vdpm gate pulse modulator enable. connect a capacitor from vdpm to gnd to set the delay time before gpm is enabled. a current source charges the capacitor on vdpm. 9 gpm_lo gate pulse modulator low voltage input. place a 0.47f decoupling capacitor close to gpm_lo pin. 10 avdd dcp and vcom amplifier high voltage analog supply. place a 0.47f decoupling capacitor close to avdd pin. 11 scl i 2 c compatible clock input lx fb comp pgnd avdd avdd vin vin scl sda avdd boost controller gpm vflk vgh vgh gpm en dcp vghm avdd pos out v com rset avdd sw avdd von sw freq sequencer re voff v com op ss ce vdpm gpm_lo voltage detector avdd vin vin vdiv cd2 reset reset neg thermal pad vlogic l1 10h c4,5,6 30f r1 73.2k r2 8.06k c20 15nf r12 5.5k c17 1nf c14 100pf r5 100k c18 0.47f r14 85k r15 115k open c26 1nf r16 10k c11 0.1f c10 47nf c8 47nf c9 1f c12 1f c28 0.1f c15 1f c16 1f vgh r26 100k r22 22k c1,2 20f r9 10k 133k r8 r7 83k c19 0.47f r6 1k c32 0.1f d1 d4 d2 d3 z1 q1 c7 0.1f
isl97649b 3 fn7927.0 december 5, 2011 12 sda i 2 c compatible serial bidirectional data line 13 pos vcom positive amplifier non-inverting input 14 rset dcp sink current adjustment pin. connect a resistor between this pin and gnd to set the re solution of dcp output voltage. 15 vout vcom amplifier output 16 neg vcom negative amplifier non-inverting input 17 vdiv voltage detector threshold. connect to the center of a resistive divider between v in and gnd. 18 nc not connected 19 reset voltage detector reset output 20 nc not connected 21 cd2 voltage detector rising edge delay. connect a capacitor between this pin and gnd to set the rising edge delay. 22 nc not connected 23 ss boost converter soft-start. conne ct a capacitor between this pin and gnd to set the soft-start time. 24 comp boost converter compensation pin. connect a series resistor and capacitor between this pin and gnd to optimize transient response and stability. 25 freq boost converter frequency select. pull to logic high to op erate boost at 1.2mhz. connect th is pin to gnd to operate boost at 600khz. 26 vin ic input supply. connect a 0.1f decoupling capacitor close to this pin. 27 lx avdd boost converter switching node 28 en avdd enable pin pin descriptions (continued) pin# symbol description ordering information part number (notes 1, 2, 3) part marking v in range (v) temp range (c) package (pb-free) pkg. dwg. # isl97649birz 97649 birz 2.5 to 5.5 -40 to +85 28 ld 4x5 qfn l28.4x5a ISL97649BIRTZ-EVALZ evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl97649b . for more information on msl please see tech brief tb363 .
isl97649b 4 fn7927.0 december 5, 2011 absolute maximum rating s thermal information re, vghm, gpm_lo, and vgh to gnd . . . . . . . . . . . . . . . . . . . -0.3 to +36v lx, avdd, pos, out to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18v voltage between gnd and pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v all other pins to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 1kv thermal resistance ja (c/w) jc (c/w) 4 x 5 qfn package (notes 4, 5) . . . . . . . . . 38 4.5 ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c functional junction temperature . . . . . . . . . . . . . . . . . . . .-40c to +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature during soldering. . . . . . . . . . . . . . . . . . . . . . . . . +260c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = enable = 3.3v, a vdd =8v, v on =24v, v off = -6v. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 6) typ (note 7) max (note 6) units general vin v in supply voltage range 2.5 3.3 5.5 v i s_dis v in supply currents when disabled vin isl97649b 5 fn7927.0 december 5, 2011 gate pulse modulator v gh vgh voltage 733 v v ih_vdpm v dpm enable threshold 1.13 1.215 1.30 v i vgh vgh input current vflk = 0 125 a re = 100k , vflk = vin 27.5 a v gpm_lo gpm_lo voltage 2vgh-2 v i gpm_lo vgpm_lo input current -2 0.1 2 a vce th1 ce threshold voltage 1 0.6xvin 0.8xvin v vce th2 ce threshold voltage 2 1.215 v i ce ce current 100 a r vghm_pd vghm pull-down resistance 1.1 k ? r onvgh vgh to vghm on resistance 23 ? idpm vdpm charge current 10 a supply monitor v ih_vdiv vdiv high threshold vdiv rising 1.265 1.280 1.295 v v il_vdiv vdiv low threshold vdiv falling 1.21 1.222 1.234 v vth cd2 cd2 threshold voltage 1.200 1.217 1.234 v i cd2 cd2 charge current 10 a r il_reset reset pull-down resistance 650 ? t delay_reset reset delay on rising edge 121.7k* cd s vcom amplifier: r load =10k, c load = 10pf, unless otherwise stated i s_com vcom amplifier supply current 0.7 1.08 ma v os offset voltage 2.5 15 mv i b noninverting input bias current 0 na cmir common mode input voltage range 0avdd v cmrr common-mode rejection ratio 60 75 db psrr power supply rejection ratio 70 85 db v oh output voltage swing high i out (source) = 0.1ma avdd - 1.39 mv i out (source) = 75ma avdd - 1.27 v v ol output voltage swing low i out (sink) = 0.1ma 1.2 mv i out (sink) = 75ma 1 v i sc output short circuit current pull up 150 225 ma pull down 150 200 ma sr slew rate 25 v/s bw gain bandwidth -3db gain point 20 mhz electrical specifications v in = enable = 3.3v, a vdd =8v, v on =24v, v off = -6v. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 6) typ (note 7) max (note 6) units
isl97649b 6 fn7927.0 december 5, 2011 digital controlled potentiometer set vr set voltage resolution (note 12) 8 bits set dnl set differential nonlinearity (notes 8, 9, 14) t a = +25c - - 1 lsb set zse set zero-scale error (note 10,14) t a = +25c - - 2 lsb set fse set full-scale error (note 11,14) t a = +25c - - 8 lsb i rset rset current - 100 a avdd to set avdd to set voltage attenuation - 1:20 - v/v fault detection threshold v uvlo undervoltage lock-out threshold pv in rising 2.25 2.33 2.41 v pv in falling 2.125 2.20 2.27 v ovp avdd boost overvoltage protection off threshold to shut down ic (note 13) 15.0 15.5 16.0 v t off thermal shut-down all channe ls temperature rising 153 c power sequence timing i ss boost soft-start current 3 5.5 8 a electrical specifications v in = enable = 3.3v, a vdd =8v, v on =24v, v off = -6v. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 6) typ (note 7) max (note 6) units serial interface specifications for scl and sda, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 14) typ (note 7) max (note 14) units f scl scl frequency (note 6) 400 khz t in pulse width suppression time at sda and scl inputs (note 6) any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v in , until sda exits the 30% to 70% of v in window. 480 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v in during the following start condition. 480 ns t low clock low time measured at 30% of v in crossing. 480 ns t high clock high time measured at 70% of v in crossing. 400 ns t su:sta start condition set-up time scl rising edge to sda falling edge, both crossing 70% of v in . 480 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v in to scl falling edge crossing 70% of v in . 400 ns t su:dat input data set-up time from sda exiting 30% to 70% of v in window to scl rising edge crossing 30% of v in . 40 ns t hd:dat input data hold time from scl rising edge crossing 70% of v in to sda entering 30% to 70% of v in window. 0ns t su:sto stop condition set-up time from scl rising edge crossing 70% of v in to sda rising edge crossing 30% of v in . 400 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge, both crossing 70% of v in . 400 ns c scl capacitive on scl 5pf
isl97649b 7 fn7927.0 december 5, 2011 c sda capacitive on sda 5pf t wp non-volatile write cycle time 25 ms eeprom endurance t a = +25c 1 kcyc eeprom retention t a = +25c 88 khrs notes: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. 7. typical values are for t a = +25c and v in = 3.3v. 8. lsb = i v 255 - v 1 i / 254. v 255 and v 1 are the measured voltages for the dcp regist er set to ff hex and 01 hex, respectively. 9. dnl = i v i+1 - v i i / lsb-1, 10. zs error = (v 1 - vmax)/lsb. vmax = (vavdd * r2) * [1-2 * r1/(256 * 20 * rset)]/(r1 + r2) 11. fs error = (v 255 - vmin)/lsb. vmin = (vavdd * r2) * [1-256 * r1/(256 * 20 * rset)]/(r1 + r2) 12. established by design. not a parametric spec. 13. boost will stop switching as soon as boost output reaches ovp threshold. 14. compliance to limits is assure d by characterization and design. serial interface specifications for scl and sda, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 14) typ (note 7) max (note 14) units i 1 255 , []
isl97649b 8 fn7927.0 december 5, 2011 typical performance curves figure 1. a vdd efficiency vs ia vdd figure 2. a vdd load regulation vs ia vdd figure 3. a vdd line regulation vs v in figure 4. boost converter transient response figure 5. gpm circuit waveform figure 6. gpm circuit waveform 76 78 80 82 84 86 88 90 92 0 50 100 150 200 250 300 350 f osc = 600khz f osc = 1.2mhz ia vdd (ma) efficiency (%) v in = 3.3v v out = 8.06v -0.04 -0.03 -0.02 -0.01 0.00 50 100 150 200 250 f osc = 600khz f osc = 1.2mhz ia vdd (ma) v in = 3.3v v out = 8.06v load regulation (%) 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) ia vdd = 150ma a vdd (v) vghm vghm
isl97649b 9 fn7927.0 december 5, 2011 figure 7. gpm circuit waveform figure 8. gpm circuit waveform figure 9. v ghm follows v gh when the system powers off figure 10. vcom rising slew rate typical performance curves (continued) vghm vghm vghm
isl97649b 10 fn7927.0 december 5, 2011 applications information enable control with vin > uvlo, all functions in isl97649b are shut down when the enable pin is pulling down. when the voltage at the enable pin reaches h threshold, the whole isl97649b is on. frequency selection the isl97649b switching frequenc y can be user selected to operate at either a constant 600khz or 1.2mhz. lower switching frequency can save power dissipation when the boost load is very low and the device is operating in deep discontinuous mode. higher switching frequency can allow the use of smaller external components like inductors and output capacitors. higher switching frequency will get higher efficiency within some loading ranges, depending on v in , v out , and external components, as shown in figure 1. connecting the freq pin to gnd sets the pwm switching frequency to 600khz. connecting the freq pin to v in sets the pwm switching frequency to 1.2mhz. soft-start soft-start is provided by an inte rnal current source to charge the external soft-start capacitor. the isl97649b ramps up the current limit from 0a to full value as voltage at the ss pin ramps from 0 to 0.8v. hence, the soft-start time is 3.2ms when the soft- start capacitor is 22nf and is 6.8ms for 47nf and 14.5ms for 100nf. operation the boost converter is a current mode pwm converter operating at either 600khz or 1.2mhz. it ca n operate in both discontinuous conduction mode (dcm) at lig ht load and in continuous conduction mode (ccm). in cont inuous conduction current mode, current flows continuously in the inductor during the entire switching cycle in steady-state operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. the boost regulator uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback, and slope compensation. a comp arator looks at the peak inductor current, cycle by cycle, and terminates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network on the order of 60k is recommended. the boost converter output voltage is determined by equation 2: the current through the mosfet is limited to 1.5a peak . this restricts the maximum output current (average) based on equation 3: where i l is peak-to-peak inductor ripple current, which is set by equation 4: where f s is the switching frequency (600khz or 1.2mhz). capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converter. a cera mic capacitor with capacitance larger than 10f is recommende d. the voltage rating of the input capacitor should be larger than the maximum input voltage. table 1 shows some recommended input capacitors. inductor the boost inductor is a critical part that influences the output voltage ripple, transient respon se, and efficiency. values of 3.3h to 10h are used to match the internal slope compensation. the inductor must be able to handle the average and peak currents shown in equation 5: table 2 shows some recommended inductors for different design considerations. rectifier diode a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode should be higher than the maximum output v boost v in ----------------- 1 1d ? ------------ - = (eq. 1) v boost r 1 r 2 + r 2 -------------------- v fb = (eq. 2) table 1. boost converter input capacitor recommendations capacitor size mfg part number 10f/6.3v 0603 tdk c1608x5r0j106m 10f/16v 1206 tdk c3216x7r1c106m 10f/10v 0805 murata grm21br61a106k 22f/10v 1210 murata grb32er61a226k table 2. boost inductor recommendations inductor dimensions (mm) mfg part number design consideration 10h/ 4apeak 8.3x8.3x4.5 sumida cdr8d43- 100nc efficiency optimization 6.8h/ 1.8apeak 5.0x5.0x2.0 tdk plf5020t- 6r8m1r8 10h/ 2.2apeak 6.6x7.3x1.2 cyntec pcme061b- 100ms pcb space /profile optimization i omax i lmt i l 2 -------- ? ?? ?? v in v o -------- = (eq. 3) i l v in l -------- d f s --- - = (eq. 4) i lavg i o 1d ? ------------ - = i lpk i lavg i l 2 -------- + = (eq. 5)
isl97649b 11 fn7927.0 december 5, 2011 voltage. the rectifier diode must meet the output current and peak inductor current requirements. table 3 shows some recommendations for boost converter diode. output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components (equation 6): 1. voltage drop due to inductor ripple current flowing through the esr of output capacitor. 2. charging and discharging of output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capa citor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in equation 6 assumes the effective value of the capacitor at a particular voltage and not the manufacturer?s stated value, measured at 0v. table 4 shows some recommendations for output capacitors. compensation the boost converter of isl97649b can be compensated by an rc network connected from the co mp pin to ground. a 15nf and 5.5k rc network is used in th e ISL97649BIRTZ-EVALZ evaluation board. the larger-value resistor and lower-value capacitor can lower the transient overshoot, but at the expense of loop stability. supply monitor circuit the supply monitor circuit monitors the voltage on vdiv and sets the open-drain output reset lo w when vdiv is below 1.28v (rising) or 1.22v (falling). there is a delay on the rising edge, controlled by a capacitor on cd2. when vdiv exceeds 1.28v (rising), cd2 is charged up from 0v to 1.217v by a 10a current source. when cd2 exceeds 1.217v, reset goes tri-state. when vdiv falls below 1.22v, reset becomes low, with a 650 pull-down resistance. delay time is controlled as shown in equation 7: for example, delay time is 12.17ms if cd2 = 100nf. figure 11 shows the supply mo nitor circuit timing diagram. gate pulse modulator circuit the gate pulse modulator circ uit functions as a three-way multiplexer, switching vghm between ground, gpm_lo, and vgh. voltage selection is provided by digital inputs vdpm (enable) and vflk (control). high-to-low delay and slew control are provided by external components on pins ce and re, respectively. when vdpm is low, the block is disabled, and vghm is grounded. when the input voltage exceeds uvlo threshold, vdpm starts to drive an external capacitor. when vdpm exceeds 1.215v, the gpm circuit is enabled, and the output vghm is determined by vflk, reset signal, and vgh voltage. if reset signal is high and vflk is high, vghm is pulled to vgh. when vflk goes low, there is a delay controlled by capacitor ce, following which vghm is driven to gpm_lo, with a slew rate controlled by resistor re. note that gpm_lo is used only as a reference voltage for an amplifier, and thus does not have to source or sink a significant dc current. low-to-high transition is determined primarily by the switch resistance and the external capaci tive load. high-to-low transition is more complex. consider a case in which the block is already enabled (vdpm is h). when vflk is h, if ce is not externally pulled above threshold voltage 1, pin ce is pulled low. on the falling edge of vflk, a current is passed into pin ce to charge the external capacitor up to threshold voltage 2, providing a delay that is adjustable by varying the capacitor on ce. once this threshold is reached, the output starts to be pulled down from vgh to gpm_lo. the maximum slew current is equal to 500/(re + 40k), and the dv/dt slew rate is isl/c load , where c load is the load capacitance applied to vghm. the slew rate reduces as vghm approaches gpm_lo. if ce is always pulled up to a voltage above threshold 1, zero delay mode is selected; thus, there will be no delay from flk falling to the point where vghm starts to fall. slew down currents will be identical to the previous case. at power-down, when vin falls to uvlo, vghm is tied to vgh until the vgh voltage falls to 3v. once the vgh voltage falls below 3v, vghm is not actively driven until vin is driven. figure 12 shows the vghm voltage based on v in , vgh, and reset. table 3. boost converter rectifier diode recommendations diode v r /i avg rating package mfg pmeg2010er 20v/1a sod123w nxp mss1p2u 20v/1a microsmp vishay table 4. boost output capacitor recommendations capacitor size mfg part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k v ripple i lpk esr v o v in ? v o --------------------- i o c out ------------- 1 f s --- - + = (eq. 6) t delay 121.7k cd2 = (eq. 7) vdiv reset 1.28v 1.22v 1.217v cd2 reset delay time is controlled by cd2 capacitor figure 11. supply monitor circuit timing diagram
isl97649b 12 fn7927.0 december 5, 2011 vcom amplifier the vcom amplifier is designed to control the voltage on the back plane of an lcd display. this plate is capacitively coupled to the pixel drive voltage, which alternately cycles positive and negative at the line rate for the display. thus, the amplifier must be capable of sourcing and sinking pulses of current, which can occasionally be quite large (in the range of 100ma for typical applications). the isl97649b vcom amplifier output current is limited to 225ma typical. this limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. it does not necessa rily prevent a large temperature rise if the current is maintained. (in this case, the whole chip may be shut down by the thermal trip to protect functionality.) if the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. this will happen in the s time scale in practical systems and for pulses 2 or 3 times the current limit, the vcom voltage will have settled again before the next line is processed. dcp (digitally controlled potentiometer) figure 13 shows the relationship between the register value and the resistor string of the dcp. note that the register value of zero actually selects the first step of the resistor string. the output voltage of dcp is given by equation 8: current sink figure 14 shows the schematic of the pos pin current sink. the circuit is made up of amplifier a1, transistor q1, and resistor r set , which form a voltage controlled current source. is forced to vgh when reset goes to low and vgh>3v power on delay time is controlled by c dpm slope is controlled by re delay time is controlled by ce figure 12. gate pulse modulator timing diagram vin uvlo 0 vgh reset vdpm vflk vghm threshold vgh gpm_lo power-on delay time controlled by c dpm slope is controlled by re delay time is controlled by ce vghm is forced to vgh when vin falls to uvlo and vgh >3v 1.215v v dcp registervalue 1 + 256 -------------------------------------------------- - ?? ?? a vdd 20 ------------- - ?? ?? = (eq. 8) a vdd 19r r 0 1 2 255 254 253 252 251 register value a vdd 20 v dcp figure 13. simplified schematic of digitally controlled potentiometer (dcp)
isl97649b 13 fn7927.0 december 5, 2011 the external r set resistor sets the full-scale sink current that determines the lowest output vo ltage of the external voltage divider, r 1 and r 2 . i out is calculated as shown by equation 9: the maximum value of i out can be calculated by substituting the maximum register value of 255 in to equation 9, resulting in equation 10: equation 9 can also be used to calculate the unit sink current step size by removing the register value term from it, as shown in equation 11. the voltage difference between the pos and rset pins, which are the drain and source, respecti vely, of the output transistor, should be greater than the mini mum saturation voltage for the i out( max) being used. this difference keeps the output transistor in its saturation region. the maximum voltage on the rset pin is a vdd /20, and this voltage is added to the minimum voltage difference between the v out and rset pins to calculate the minimum v out voltage, as shown in equation 12. output voltage the output voltage, v out , can be calculated with equation 13: where r l , r u and rset in equation 11 correspond to r 7 , r 8 and r 9 in the application diagram on page 2. i 2 c serial interface the isl97649b supports a bidirectional, bus-oriented protocol. the protocol defines any device that sends data on to the bus as a transmitter and the receiving devi ce as the receiver. the device controlling the transfer is a master, and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and rece ive operations. therefore, the dcp of the isl97649b operates as a slave device in all applications. the fall an d rise times of the sda and scl signals should be in the range listed in table 5. capacitive load on i 2 c bus is also specified in table 5. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. programming supply voltage to program eeprom bits, vgh must be higher than 12v when avdd is 8v. outside these conditions, writing operations may not be successful. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop condit ions (figure 15). on power-up of the isl97649b, the sda pin is in input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the dcp continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (figure 15). a st art condition is ignored during the power-up sequence and during internal non-volatile write cycles. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (figure 15). a stop condition at the end of a read operation, or at the end of a write operation to volatile bytes only, places the device in standby mode. a stop condition during a write operation to a non-volatile write byte initiates an internal non-volatile write cycle. the device enters standby mode when the internal non-volatile write cycle is completed. an acknowledge (ack) is a software convention used to indicate a successful data transfer. the tr ansmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge receipt of the eight bits of data (figure 16). the isl97649b dcp responds with an ack after recognizing a start condition followed by a valid identification byte (byte 1). if a master-receiver is involved in a transfer, it must signal the end of data transmission to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. the isl97649b releases th e dataline to allow the master to generate a stop condition. figure 14. current sink circuit a vdd r set v dcp rset pos a vdd i out r 1 r 2 v sat v set = (i out )*(r set ) = v dcp q1 a1 v out i out v dcp r set ------------- registervalue 1 + 256 -------------------------------------------------- - ?? ?? a vdd 20 ------------- - ?? ?? 1 r set ------------ - ?? ?? == (eq. 9) i out max () a vdd 20r set -------------------- = (eq. 10) i step a vdd 256 () 20 () r set () --------------------------------------------- - = (eq. 11) v out min () a vdd 20 ------------- - minimumsaturationvoltage + (eq. 12) v out r l v avdd ? r u r l + () ---------------------------- 1 registervalue 1 + 256 -------------------------------------------------- - r u 20 rset () -------------------------- - ? ?? ?? ? = (eq. 13) table 5. i 2 c interface specifications parameter min typ max units sda and scl rise time 1000 ns sda and scl fall time 300 ns i 2 c bus capacitive load 400 pf
isl97649b 14 fn7927.0 december 5, 2011 a valid identification byte (byte 1) contains 100111 as the six msbs. the 7th bit could be either 0 or 1 in the read operation, while it is the data lsb (d0) in the write operation. the lsb is in the read/write bit. its value is 1 for a read operation and 0 for a write operation (figures 17 and 18). read operation a read operation consists of one instruction byte followed by one data byte (figure 17). the master initiates a start and the identification byte with the r/w bit set to 1; the isl97649b responds with an ack; and then the isl97649b transmits the data byte. the master terminates the read operation (issues a stop condition) following the last bit of the data byte (figure 17). write operation a write operation requires a start condition followed by a valid identification byte, a data byte, and a stop condition (figure 18). after each of the two bytes, the isl97649b responds with an ack. if the data byte is also to be written to non-volatile memory, the isl97649b begins its internal write cycle to non-volatile memory. during the internal non-vo latile write cycle, the device ignores transitions at the sda an d scl pins, and the sda output is at high impedance state. when the internal non-volatile write cycle is completed, the isl97649b enters its standby state. the lsb in byte 2 determines whether the data byte is to be written to volatile and/or non-volatile memory. data protection a stop condition also acts as a protection of non-volatile memory. a valid identification byte, a data byte, and total number of scl pulses act as a pr otection of both volatile and non-volatile registers. during a write sequence, the data byte is loaded into an internal shift regist er as it is received. if byte 2 lsb is 1, the data byte is transferred to the register only. if byte 2 lsb is 0, then the stop condition initiates the internal write cycle to non-volatile memory. isl97649b programming figure 17 shows the serial data format for reading the register. figure 18 shows the serial data format for writing the register. the isl97649b uses a 6-bit i 2 c address, which is 100111xx. the complete read and write protocol is shown in figures 17 and 18. sda scl start data stop stable data stable figure 15. valid data changes, start, and stop conditions data change sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 16. acknowledge response from receiver
isl97649b 15 fn7927.0 december 5, 2011 i 2 c read and write format figure 17. i 2 c read format figure 18. i 2 c write format 6 bit address start r/w ack da ta progra m a ck data lsb sto p 10 01 1 1 0 d0 d7 d 6 d5 d4 d3 d2 d1 p a a isl24201 i 2 c w rite r/w = 0 = write r/w = 1 = read when r/w = 0 p = 0 = eeprom programming p = 1 = register write byte 1 by te 2 msb lsb m sb lsb isl97649b i 2 c write
isl97649b 16 fn7927.0 december 5, 2011 start-up sequence when vin rising exceeds uvlo, it takes 120s to read the settings stored in the chip in or der to activate the chip correctly. when vin is above uvlo and en is high, the boost converter starts up. the gate pulse modulator output vghm is held low until vdpm is charged to 1.215v. the detailed power-on sequence is shown in figure 19. en avdd vin uvlo uvlo panel normal operation vghm vghm output tied to vgh when vin falls to uvlo t ss_avdd controlled by v ss voff von vcom vdiv reset 1.280v cd2 1.217v 1.222v 1.215v vdpm gpm enabled when both 1) en = high and 2) vdpm >1.215v figure 19. isl97649b detailed power-on/power-off sequence
isl97649b 17 fn7927.0 december 5, 2011 layout recommendations the device's performance, including efficiency, output noise, transient response and control lo op stability, is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v dc and v ref bypass capacitors close to the pins. 3. reduce the loop with large ac amplitudes and fast slew rate. 4. the feedback network should sense the output voltage directly from the point of load and should be as far away from the lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at the isl97649b exposed die plate area. 6. the exposed die plate, on the underside of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissi pation to the surrounding air. 8. minimize feedback input track lengths to avoid switching noise pick-up. the ISL97649BIRTZ-EVALZ evaluation board is available to illustrate the proper layout implementation.
isl97649b 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7927.0 december 5, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl97649b to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change december 5, 2011 fn7927.0 initial release
isl97649b 19 fn7927.0 december 5, 2011 package outline drawing l28.4x5a 28 lead quad flat no-lead plastic package rev 2, 06/08 c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 5.00 (4x) 0.15 6 pin 1 index area 23 pin #1 index area 28 2.50 24x 0.50 exp. dap 8 1 22 14 28x 0.400 9 6 3.50 max 0.90 see detail "x" seating plane 0.08 0.10 c c c ( 4.80 ) ( 3.50 ) ( 28 x 0.60) (28x .250) ( 24x 0.50) ( 3.80 ) ( 2.50) 2.50 0.10 28x 0.25 a mc b 4 3.50 exp. dap 15 typical recommended land pattern detail "x" top view bottom view side view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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